One of the primary steps in the fabrication of modern semiconductor devices is the formation of a thin film on a semiconductor substrate by chemical reaction of gases. Such a deposition process is referred to as chemical vapor deposition (“CVD”). Conventional thermal CVD processes supply reactive gases to the substrate surface where heat-induced chemical reactions take place to produce a desired film. Plasma-enhanced CVD (“PECVD”) techniques, on the other hand, promote excitation and/or dissociation of the reactant gases by the application of radio-frequency (“RF”) energy to a reaction zone near the substrate surface, thereby creating a plasma. The high reactivity of the species in the plasma reduces the energy required for a chemical reaction to take place, and thus lowers the temperature required for such CVD processes as compared to conventional thermal CVD processes. These advantages are further exploited by high-density-plasma (“HDP”) CVD techniques, in which a dense plasma is formed at low vacuum pressures so that the plasma species are even more reactive.
Any of these CVD techniques may used to deposit conductive or insulative films during the fabrication of integrated circuits. For applications such as the deposition of insulation films as premetal or intermetal dielectric layers in an integrated circuit or for shallow trench isolation, one important physical property of the CVD film is its ability to completely fill gaps between adjacent structures without leaving voids within the gap. This property is referred to as the film's gapfill capability. Gaps that may require filling include spaces between adjacent raised structures such as transistor gates, conductive lines, etched trenches or the like.
As semiconductor device geometries have decreased in size over the years, the ratio of the height of such gaps to their width, the so-called “aspect ratio,” has dramatically increased. Gaps having a combination of a high aspect ratio and a small width present a challenge for semiconductor manufacturers to fill completely. In short, the challenge usually is to prevent the deposited film from growing in a manner that closes off the gap before it is filled. Failure to fill the gap completely results in the formation of voids in the deposited layer, which may adversely affect device operation, for example by trapping undesirable impurities.
One process that the semiconductor industry has developed to improve gapfill capability of insulation films uses a multistep deposition and etching process. Such a process is often referred to as a deposition/etch/deposition (“dep/etch/dep”) process. Such dep/etch/dep processes divide the deposition of the gapfill layer into two or more steps separated by a plasma etch step. The plasma etch step etches the upper corners of the first deposited film more than the film portion deposited on the sidewall and lower portion of the gap, thereby widening the gap and enabling the subsequent deposition step to fill the gap without prematurely closing it off. Typically, dep/etch/dep processes can be used to fill higher-aspect-ratio small-width gaps than a standard deposition step for the particular chemistry would allow.
Most of the early dep/etch/dep processes known to the inventors were limited to thermal CVD and PECVD processes. HDP-CVD processes generally have superior gapfill capabilities as compared to these other types of CVD processes because HDP-CVD deposition process provide for a sputtering component to the deposition process simultaneous with film growth. For this reason, HDP-CVD techniques are sometimes referred to as simultaneous dep/etch processes.
It has been found in practice, however, that while HDP-CVD processes generally have better gapfill capabilities than similar non-HDP-CVD processes, for certain gap widths there remains a limit to the aspect ratio of gaps that can be filled. Accordingly, a number of different dep/etch/dep techniques have been specifically developed for HDP-CVD processes.
One example of a previously known HDP-CVD dep/etch/dep technique is described in U.S. Pat. No. 6,030,881 (“the '881 patent”) issued jointly to Novellus and International Business Machines. The '881 patent describes an in situ HDP-CVD dep/etch/dep process performed in a single chamber. The described process transitions from deposition to etch steps by changing the gas mixture composition along with other chamber parameters.
While the '881 patent does not include details of a specific HDP-CVD dep/etch/dep process recipe, it does include several tables that identify possible ranges for various parameters in each of the deposition and etch steps of the process. The first two tables provided, Tables 1 and 2, recite the possible gas flow rates of the various gases introduced in the deposition and etch steps, respectively. According to Table 1, the deposition step flows silane, oxygen and an inert gas into the chamber at rates similar to many previously known HDP-CVD deposition processes. Table 2 then indicates that the etch step flows at least oxygen and an inert gas into the chamber along with maybe flows of either or both a reactive etch gas and silane.
Based on the parameters set forth in Table 2, it can be understood that the dep/etch/dep process disclosed in the '881 patent has a number of limitations. For example, one possible use for an HDP-CVD dep/etch/dep step in the fabrication of current and future integrated circuits is for shallow trench isolation (STI) applications. Such STI applications often provide the most challenging gapfill requirements for insulation layers especially considering that many integrated circuits now use copper and appropriate dual damascene techniques as the interconnect structure. According to Table 2, however, the '881 patent contemplates performing the etch step without any reactive etch gas (i.e., a reactive etch gas flow rate of 0 sccm). Such an etch step is a fully directional etch (i.e., an anisotropic sputter etch) that is susceptible to corner clipping problems.
Assuming a reactive etch gas (i.e., a fluorine-containing gas according to the examples listed in the patent) is used, however, Table 2 provides two possible scenarios for its use. In the first scenario, the reactive etch gas is introduced into the chamber with flows of oxygen and an inert gas (i.e., the flow of silane is 0 sccm). The inventors of the present patent have determined that transitioning from such a fluorine-containing etch step straight to a subsequent deposition step as taught in the '881 patent results in an undesirable amount of fluorine being incorporated at the interface of the first and second layers of the film and may also result in etch defects (silicon-rich pockets on the surface of the etched film that look like particles). In the second scenario, where both a reactive etch gas and silane are introduced into the HDP chamber along with flows of oxygen and an inert gas, a small amount of film deposition will occur simultaneous with the etch process thereby incorporating additional fluorine into the film.
Regardless of how such fluorine is incorporated in the film, the result is generally undesirable. In some situations the incorporated fluorine may outgas during subsequent processing steps. In other situations, the existence of fluorine in the layer may make a semiconductor manufacturer wary of the integrity of the layer.
Accordingly, while HDP-CVD dep/etch/dep processes may provide gapfill improvements over standard HDP-CVD processes, further improvements and/or alternative approaches are desirable. Such improved processes are particularly desirable in light of the aggressive gapfill challenges presented by integrated circuit designs employing minimum feature sizes of 0.10 microns and less.